As the density of circuit components has increased and components have been shrunk in size and are spaced closer together, it has become increasingly difficult to access selectively a particular buried region of the silicon wafer workpiece through the various layers that are typically superposed on the surface of the silicon wafer without undesired interference with other active regions. In the absence of special measures to compensate for some misalignment in the masks, it is difficult to maximize the yield of good chips.
In particular, in the manufacture of chips with a high density of components, it is important to have a process for providing the various metalizations necessary in such chips that tolerates some misalignment of the masks used to define the metalizations.
It is especially important to have a technology that can etch openings that have essentially vertical side walls, when the openings are to extend deeply in the surface layers. Additionally, to tolerate some misalignment in the masks used to define such openings, it is advantageous to provide protection to regions that need isolation but inadvertently lie partially in the path of the projected opening. To this end it is sometimes the practice to surround such regions with a layer of material that resists etching by the process being used to form the openings.
Accordingly, a technology that provides the desired results will need an appropriate choice both of the materials used in the layers and the particular etching process used with the materials chosen.
Dry etching, such as plasma etching and reactive ion etching, has become the technology of choice in patterning various layers that are formed over a silicon wafer as it is processed to form therein high density integrated circuit devices. This is because it is a process that not only can be highly selective in the materials it etches, but also highly anisotropic. This makes possible etching with nearly vertical side walls.
Basically, in plasma etching as used in the manufacture of silicon integrated circuit devices, a silicon wafer on whose surface has been deposited various layers is positioned on a first electrode in a chamber that also includes a second electrode spaced opposite the first. As a gaseous medium consisting of one or more gases is flowed through the chamber, an r-f voltage, which may include components at different frequencies, is applied between the two electrodes to create a discharge that ionizes the gaseous medium and forms a plasma that etches the wafer. By appropriate choice of the gases of the gaseous medium and the parameters of the discharge, selective and anisotropic etching is achieved.
Various gaseous media has been used in the past for such etching, depending on the materials being etched, the selectivity that is needed, the profile sought for the side walls of the pattern being etched, and the rate desired for the etching step.
While elaborate theories have been developed to explain the plasma etching process, in practice most such processes have been developed largely by experimentation involving trial and error because of the relatively poor predictability of results otherwise.
Moreover, because of the number of variables involved and because most etching processes depend critically not only on the particular materials to be etched but also on the desired selectivity and anisotropy, such experimentation can be time consuming and success often depends on chance.
A dielectric layer, typically of a deposited oxide of silicon, such as a glassy silicate, is in common use in integrated circuits. A oxide of this kind is also used often in conjunction with a form that has been doped with either phosphorus or boron, or a mixture of both. It is known that the addition of the boron and phosphorus to such oxides can make such oxides more readily etched than the undoped form.
For example, in U.S. Pat. No. 5,022,958, issued on Jun. 11, 1991, there is described a process for manufacturing silicon integrated circuit devices that uses both a silicate glass in an undoped form (TEOS) and a silicate glass in a form doped both with boron and phosphorus (BPTEOS). For the selective etch of BPTEOS in preference to TEOS, a plasma etching process that employs a gaseous medium that includes both CHF.sub.3 (Freon 23) and argon is used to readily etch windows in the BPTEOS layers with little effect on the TEOS layers.
Additionally, U.S. Pat. No. 5,021,121, issued on Jun. 4, 1991, teaches that an oxide of silicon doped with phosphorus is more readily etched than the undoped form by a plasma generated from a mixture of CHF.sub.3 and an inert gas, argon or helium being the specific inert gases mentioned.
However, for use with submicron devices, an even higher degree of selectivity and anisotropy than those prior art processes provide would be advantageous and the invention is directed at such end.